View MC68160_5157.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Order this document by MC68160/D
Enhanced Ethernet Transceiver
The MC68160, B and C Enhanced Ethernet Interface Circuit is a BiCMOS device which supports both IEEE 802.3* Access Unit Interface (AUI) and 10BASE-T Twisted Pair (TP) Interface media connections through external isolation transformers. It encodes NRZ data to Manchester data and supplies the signals which are required for data communication via 10BASE-T or AUI interfaces. The MC68160, B and C gluelessly interface to the Ethernet controller contained in the MC68360 Quad Integrated Communications Controller (QUICC) device. The MC68160 also interfaces easily to most other industry-standard IEEE 802.3 LAN controllers.** Prior to twisted pair data reception, Smart Squelch circuitry qualifies input signals for correct amplitude, pulse width, and sequence requirements.
MC68160 MC68160B MC68160C
ENHANCED ETHERNET INTERFACE TRANSCEIVER
SEMICONDUCTOR TECHNICAL DATA
* * * * * * * * * * * *
Automatic Twisted Pair Wiring Polarity Fault Detection and Correction Option Automatic Port Selection Option with Status Output Driver Pre-emphasis for Twisted Pair Output Data Crystal Controlled Clock Oscillator or External Clock Generator Option
52 1
Digital Phase-Locked-Loop (DPLL) Timing Recovery and Data Decoding Standby Mode with Reduced Power Consumption Twisted Pair Signal Quality Error (Heartbeat) Test Option Diagnostic Local Loop Back Option Transmit, Receive and Collision Detection Status Output Full-Duplex Operation Option on Twisted Pair Port Twisted Pair Jabber Detection and Status Output Link Integrity Testing and Status Output ORDERING INFORMATION
Device MC68160FB MC68160CFB TA = 0 to + 70C TA = -40 to + 85C Operating Temperature Range Package TQFP-52 TQFP-52 TQFP-52 FB SUFFIX PLASTIC PACKAGE CASE 848D (TQFP-52)
** MC68160B does not support all IEEE 802.3 specifications over extended ** temperature range. Exceptions noted in specifications. ** MC68160B, C only support Motorola controllers
MC68160BFB
The sale and use of this product is licensed under technology covered by one or more Digital Equipment Corporation patents.
(c) Motorola, Inc. 1997
Rev 1
MOTOROLA ANALOG IC DEVICE DATA
1
MC68160 MC68160B MC68160C
Figure 1. 10Base-T Interface Block Diagram
RX RCLK MFILT RXLED RENA CLLED Pulse Conditioner Pulse Conditioner Mux Pulse Conditioner Manchester Encoder 20 MHz Osc /2 Jabber Control Mode Select Driver Pre-emphasis Control Link Pulse Control Collision Detector Control Receiver Squelch Squelch Test Circuit Mux Receiver Mux Carrier Detect Mux Noise Reject Filter Collision Detect Noise Reject Filter ARX-
Manchester Decoder
Mux
Data Receiver
ARX+
ATX- ATX+ Twisted Pair Polarity Error Control
TENA TX X1 X2 TCLK
CS0 CS1 CS2 TPEN APORT TPAPCE TPSQEL TPFULDL LOOP
TPJABB
TPTX+ TPTX-
TPLIL
TPSQEL
TPRX-
TPRX+ TPPLR
This device contains 20,000 active transistors.
2
MOTOROLA ANALOG IC DEVICE DATA
AUI INTERFACE
SIA INTERFACE
CLSN TXLED
ACX+ ACX-
MC68160 MC68160B MC68160C Enhanced Ethernet Serial Transceiver
Table 1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Controller Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUI Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Twisted Pair Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator and Frequency Multiplier Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Select Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Indicator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 4 5 5 6 6
Table 2. Controller Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Controller Independent Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Supply DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TTL/CMOS Input and Output DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Twisted Pair Input and Output DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 AUI Input and Output DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
External Clock Input (X1) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Phase Locked Loop Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Transmit Switching Characteristics (Motorola Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Receive Switching Characteristics (Motorola Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Transmit Switching Characteristics (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Receive Switching Characteristics (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Transmit Switching Characteristics (Fujitsu Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Receive Switching Characteristics (Fujitsu Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Transmit Switching Characteristics (National Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Receive Switching Characteristics (National Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TP Transmit Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TP Transmit Jabber Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TP Transmit Signal Quality Error Test Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TP Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TP Receive Link Integrity Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TP Collision Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TP Full Duplex Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUI Transmit Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUI Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jabber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Polarity Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop Back Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selection of Crystal and External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Filter Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T Filter and Transformer Choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUI Transformer Choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 12 14 14 15 15 16 16 18 20 20 21 21 23 23 24 24 25 26 26 26 26 26 26 26 27 27 27 27
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
MOTOROLA ANALOG IC DEVICE DATA
3
MC68160 MC68160B MC68160C
Table 1. Pin Function Descriptiont
Pin(s) Symbol Type Name/Function
CONTROLLER INTERFACE
1 2 RENA RX O TTL/CMO O TTL/CMOS Receive Enable Output: Indication of the presence of network activity, synchronous to RCLK. In the standby mode, RENA is driven to the high impedance state. Receive Data Output: Recovered data, synchronous to RCLK. Following a reset operation, 100 ms should be allowed before attempting to read data processed by the MC68160, B and C. This delay is needed to insure that the receive phase locked loop is properly synchronized with incoming data. In the standby mode, RX is driven to the high impedance state. Transmit Clock Output CMOS/TTL Output: TCLK provides a symmetrical clock signal at 10 MHz for reference timing of data to be encoded. In the standby mode, TCLK is driven to the high impedance state. Transmit Enable Input: Input signal synchronous to TCLK which enables data transmission on the active port. An internal pull-down resistor is provided so that the input is low under no connect conditions. (This resistor is removed in the standby mode). If TENA is asserted at the conclusion of a reset operation, it must first be deasserted and then reasserted before data transmission can occur. In the standby mode, TENA is driven to the high impedance state. Receive Clock Output: Recovered clock. In the standby mode, RCLK is driven to the high impedance state. Collision Output: In the AUI mode, indicates the presence of signals at the ACX+ and ACX- terminals which meet threshold and pulse width requirements. In the TP mode, indicates simultaneous transmit and receive activity, a heartbeat (SQE Test) signal was generated, or the jabber timer has expired. In the standby mode, CLSN is driven to the high impedance state. Transmit Data Input: Input signal synchronous to TCLK which provides NRZ serial data to be Manchester encoded. In the standby mode, TX is driven to the high impedance state.
48
TCLK
O TTL/CMOS I TTL
49
TENA
50 51
RCLK CLSN
O TTL/CMOS O TTL/CMOS
52
TX
I TTL
AUI INTERFACE
21 22 23 24 25 26 ACX- ACX+ ARX- ARX+ ATX- ATX+ I AUI Differential Collision Inputs: These inputs are connected to a pair of internally biased line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to detect the line activity. Signals at ACX+/- have no effect on data path functions. AUI Differential Receiver Inputs: These inputs are connected to a pair of internally biased line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to detect the line activity, and a data receiver with no offset for Manchester Data reception. AUI Differential Transmit Outputs : This line pair is intended to operate into terminated transmission lines. For TX signals meeting setup and hold time to TCLK when TENA is previously asserted, Manchester encoded data is outputted at ATX+/-. When operating into a 78 terminated transmission line, signaling meets the required output levels and skew for IEEE-802.3 drop cables. When the 10BASE-T port is automatically or manually selected, the AUI outputs are driven to a low power standby state in which the outputs deliver a balanced high state voltage.
I
O
TWISTED PAIR INTERFACE
31 32 TPRX- TPRX+ I Twisted Pair Differential Receiver Inputs: These inputs are connected to a receiver with Smart Squelch capability which only allows differential receive data to pass as long as the input amplitude is greater than a minimum signal threshold level and a specific pulse sequence is received. This assures a good signal to noise ratio while the signal pair is active by preventing crosstalk and impulse noise conditions from activating the receive function. Twisted Pair Differential Transmitter Outputs: These lines have pre-distortion drive capability and are intended to drive terminated twisted pair transmission lines. When the AUI port is manually selected, the 10BASE-T outputs are driven to a low power standby state in which the outputs deliver a balanced high state voltage. However, when the AUI port is automatically selected, the 10BASE-T outputs remain active.
36 37
TPTX- TPTX+
O
NOTE:
The sense of the controller interface pins will change, depending on the controller selected.
4
MOTOROLA ANALOG IC DEVICE DATA
MC68160 MC68160B MC68160C
Table 1. Pin Function Description (continued)
Pin(s) Symbol Type Name/Function
OSCILLATOR AND FREQUENCY MULTIPLIER
12 16 MFILT X1 C I/C CMOS Frequency Multiplier Filter Connection Point: An external resistor capacitor filter must be attached to this pin. Oscillator Inverter Input and Crystal Connection Point: When connected for crystal oscillator operation, the frequency of the clock which appears at TCLK is half that of the crystal oscillator. As an option, instead of connecting to a crystal, X1 may be driven from an external 20 MHz CMOS compatible clock generator. Oscillator Inverter Output and Crystal Connection Point: This pin is used only for the connection of an external crystal and capacitor. It must be left unconnected if X1 is driven by an external CMOS Clock generator.
17
X2
O/C CMOS
MODE SELECT
3 4 5 6 CS0 CS1 CS2 LOOP I TTL Mode Select: The logic states applied to these pins select the appropriate interface for the desired IEEE-802.3 controller or enable the standby mode. When the standby mode is selected, the MC68160, B and C power supply current is greatly reduced. Additionally, in the standby mode, all of the controller inputs and outputs are driven to the high impedance state. Diagnostic Loopback: Asserting this function causes serial NRZ data at the TX input to be Manchester encoded and then looped back through the Manchester decoder, appearing at the RX output. This diagnostic loopback function operates independent of Twisted Pair (TP) or Access Unit Interface (AUI) port connectivity or activity. Neither the TP port nor the AUI port transmits data from the controller while diagnostic loopback is selected. Likewise, the controller interface receives data neither from the TP nor the AUI receivers while in this mode. The polarity fault detection and link integrity functions are not inhibited by the diagnostic loopback mode. If otherwise enabled, they continue to function. If the twisted pair port is selected, and TPSQEL is driven to the low logic state, a collision detect pulse is delivered following each transmission to simulate the twisted pair SQE test. Automatic Port Selection Enable: When high, MC68160, B and C will automatically select the TP or AUI port based on the presence or absence of valid link beats or frames at the TP receive input. If the AUI port is automatically selected, the MC68160, B and C will continue to produce link pulses for the TP port. Changing ports requires approximately 1.0 ms to allow the circuitry for the new port to resume normal operation. The power consumption is minimized in the circuitry associated with the unselected port. Twisted Pair Signal Quality Error Test Enable: Forcing this pin low enables testing of the internal TP collision detect circuitry after each transmit operation to the TP media. This function provides a simulated collision to as much of the MC68160, B and C collision detect circuitry as possible without affecting the attached twisted pair channel. A normal SQE test results in a high logic state at the CLSN controller interface pin which begins 6 to 16-bit times after the last transition of a transmitted signal and continues for 5 to 15-bit times. (When the AUI port is selected, SQE test signals are generated by the coaxial cable transceiver and delivered to the controller via the MC68160, B and C ACX+/- receive inputs) Twisted Pair Full Duplex Mode Select: Forcing this pin low allows simultaneous transmit and receive operation on the twisted pair port without an indicated collision. This pin is not to be asserted with LOOP as a test mode is enabled that disrupts normal operation. Twisted Pair Automatic Polarity Correction Enable: When TPAPCE is high, automatic polarity correction is enabled, and MC68160, B and C will internally correct for a polarity fault on the receive circuit. Additionally, when TPAPCE is high, the presence of a polarity fault is indicated on TPPLR. Twisted Pair Port Enable: If APORT is low, TPEN is an input which determines whether the AUI port (TPEN low) or TP port (TPEN high) will be manually selected. If the AUI port is manually selected, the MC68160, B and C will not produce link pulses for the TP port. If APORT is high, TPEN is an output which will indicate which port has been automatically selected by driving TPEN low (for AUI) or high (for TP). In its output mode TPEN can sink 10 mA in the low output state and source 10 mA in the high output state. (See Pin 9 Description.) Changing ports requires approximately 1.0 ms to allow the circuitry for the new port to resume normal operation. The power consumption is minimized in the circuitry associated with the unselected port. In the standby mode, this pin is driven to the high impedance state.
I TTL
9
APORT
I TTL
27
TPSQEL
I TTL
28
TPFULDL
I TTL I TTL
29
TPAPCE
46
TPEN
I/O TTL (TTL/CMOS)
MOTOROLA ANALOG IC DEVICE DATA
5
MC68160 MC68160B MC68160C
Table 1. Pin Function Description (continued)
Pin(s) Symbol Type Name/Function
STATUS INDICATOR
40 TXLED O TTL/CMOS Transmit Status LED Driver Output: This pin indicates the transmit status of the currently selected TP or AUI port. When there is no transmit activity detected, an internal pull-up takes this pin to its normal off (high) state. When transmit activity is detected, the LED driver turns on. In its on state, TXLED flashes the LED by driving low at approximately 10 Hz at a 50% duty cycle. In the standby mode, this output is driven to the high impedance state. Receive Status LED Driver Output: This pin indicates the receive status of the currently selected TP or AUI port. When there is no receive activity detected, an internal pull-up takes this pin to its normal off (high) state. When receive activity is detected, the LED driver turns on. In its on state, RXLED flashes the LED by driving low at approximately 10 Hz at a 50% duty cycle. In the standby mode, this output is driven to the high impedance state. Collision Status LED Driver Output: This pin indicates the collision status of the currently selected TP or AUI port. When there is no collision activity detected, an internal pull-up takes this pin to its normal off (high) state. When collision activity is detected, the LED driver turns on. In its on state, CLLED flashes the LED by driving low at approximately 10 Hz at a 50% duty cycle. In the standby mode, this output is driven to the high impedance state. Twisted Pair Link Integrity Output: This output is driven to the low output state to indicate good link integrity on the TP port during TP mode. It is deasserted (high) when link integrity fails in TP mode. The TPLIL output is driven to the high impedance state when the AUI port is selected. In the standby mode, this output is also driven to the high impedance state. Twisted Pair Polarity Error Output: If TPAPCE is high and the wires connected to the Twisted Pair Receiver Inputs (TPRX+, TPRX-) are reversed, TPPLR will be driven to the low logic state to indicate the fault. TPPLR remains low when the MC68160, B and C has automatically corrected for the reversed wires. If the twisted pair link integrity tests fail, this output will be driven to the high logic state. When the AUI mode is selected this output is driven to the high impedance state. In the standby mode, this output is also driven to the high impedance state. Twisted Pair Jabber Output: This pin is driven high to indicate a jabber condition at the TPTX+/- outputs. (Jabber condition also causes CLLED to be driven alternately to the high and low output levels). TPJABB is driven to the low output state when no jabber condition is present. When the AUI mode is selected this output is driven to the high impedance state. In the standby mode, this output is also driven to the high impedance state.
41
RXLED
O TTL/CMOS
42
CLLED
O TTL/CMOS
43
TPLIL
O TTL/CMOS
44
TPPLR
O TTL/CMOS
45
TPJABB
O TTL/CMOS
POWER SUPPLY AND GROUND
10 11 13 14 15 20 7 8 18 19 30 33 34 35 38 39 47
NOTE:
VDDDIV VDDFM GNDFM GNDVCO VDDVCO GNDSUB VDDDIG GNDDIG VDDDIG GNDDIG VDDANA GNDANA GNDPWR VDDPWR VDDPWR GNDPWR GNDCTL
Frequency Divider Supply Pin Frequency Multiplier Supply and Ground Pins Voltage Controlled Oscillator Ground and Supply Pins Substrate Ground Pin Digital Supply and Ground Pins
Analog Supply and Ground Pins Power Supply and Ground Pins
Controller Interface Ground Pin
Power and ground pins are not connected internally. Failure to connect externally may cause malfunction or damage to the IC.
6
MOTOROLA ANALOG IC DEVICE DATA
MC68160 MC68160B MC68160C
Table 2. Controller Interface Selection
Motorola Transceiver MC68160, B and C (EESTTM) CS0 CS1 CS2 Pin TCLK TX TENA RCLK RX RENA CLSN LOOP1 Pin TCLK TX TENA RCLK RX RENA CLSN N.A. Motorola Controller2 MC68360 (QUICCTM) 1 1 0 Sense High High High High High High High High Pin TXC TXD RTS RXC RXD CRS CDT LPBK Intel4 Controllers 82586, 82590, 82593, 82596 0 1 0 Sense Low High Low Low High Low Low Low Pin TCKN TXD TEN RCN RXD XCD XCOL LBC Fujitsu4 Controllers 86950 (EtherstarTM) 86960 (NICETM) 1 0 0 Sense Low High High Low High High Low High Pin TXC TXD TXE RXC RXD CRS COL LPBK National4 Controllers 8390, 83C690, 83932B (SONICTM) 0 0 0 Sense High High High High High High High High
NOTES: 1. Although LOOP input is not ordinarily classifed as a controller pin, it is included in this table because its sense varies according to the controller used. 2. The Motorola controller interface contained in the MC68360 (QUICCTM) is compatible with the AMD 7990 (LANCETM) and 79C900 (ILACCTM) controllers. 3. The pin sense is shown from the perspective of the identified controller pin. 4. Supported only by MC68160.
Table 3. Controller Independent Mode Selection
Pin CS0 CS1 CS2 Standby Mode 1 1 1 Reserved 0 1 1 Reserved 1 0 1 Reserved 0 0 1
NOTE: In standby mode, the MC68160, B, C consumes less power supply current than in any other mode. Additionally, in the standby mode, all of the controller inputs and outputs are driven to the high impedance state. When the standby mode is deasserted, an internal reset pulse of approximately 6.0 s duration is generated. Following a period of operation in the standby mode, the time required to insure stable data reception is approximately 100 ms.
Figure 2. Applications Block Diagram
ATX+ ATX- ARX+ TCLK ARX- TX ACX+ TENA ACX- RCLK RX RENA TPTX+ CLSN TPTX- TPRX+ TPRX- TPTX+ ATX+ ATX- ARX+
Pulse Transformers
ARX- ACX+ ACX-
DB-15 Connector
LAN Controller
MC68160, B, C
Filters and Pulse Transformers
TPTX- TPRX+ TPRX-
RJ-45 Connector
MOTOROLA ANALOG IC DEVICE DATA
7
MC68160 MC68160B MC68160C
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Characteristic Storage Temperature Range Power Supply Voltage Range Analog Digital Voltage on any TTL compatible input pin with respect to Ground Voltage on TPRX, ARX, or ACX input pins with respect to Ground Differential Voltage on TPRX, ARX, or ACX Input Pins
NOTE:
Symbol Tstg VDDA VDDD V
Min - 65 - - - 0.5 - 0.5
Max 150 7.0 7.0 VDD + 0.5 6.0 6.0
Unit C V V
VDIFF
- 6.0
V
Stresses in excess of the Absolute Maximum Ratings can cause permanent damage to the device. Functional operation of the device is not implied at these or any other conditions in excess of those indicated in the operation sections of this data sheet. Exposure to Absolute Maximum Ratings conditions for extended periods can adversely affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Characteristic Power Supply Voltage Range Power Supply Ripple (20 kHz to 100 kHz) Power Supply Impulse Noise (Either Polarity) Ambient Operating Temperature Range (MC68160, MC68160C) Ambient Operating Temperature Range (MC68160B) ARX/ACX Input Differential Rise and Fall Time (see Figure 39) ARX Pair Idle Time after Transmission (see Figure 39) Symbol VDD - - TA TA t260 t265 Min 4.75 - - 0 -40 2.0 8.0 Max 5.25 50 100 70 85 10 - Unit V mV mV C C ns s
ESD
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Motorola employs a Human Body Model (HBM) and a Charged Device Model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD has been adopted for the CDM, however, a standard HBM (resistance = 1500 capacitance - 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using the circuit parameters contained in this specification. ESD threshold voltage is designed to 700 kV Human Body Model.
DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended
ambient operating temperature and power supply voltage ranges.) Characteristic POWER SUPPLY Undervoltage Shutdown Threshold Power Supply Current - IDD - - Standby Mode - - - - 145 - 4.4 200 5.0 V mA Symbol Test Conditions Min Typ Max Unit
8
MOTOROLA ANALOG IC DEVICE DATA
MC68160 MC68160B MC68160C
DC ELECTRICAL CHARACTERISTICS (TA = 25C, VCC = 5.0 V 5%. Unless otherwise noted, minimum and maximum
limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160, B, C except where noted.) Characteristic TTL COMPATIBLE INPUTS TTL Compatible Input Voltage Low State High State Input Current TTL Compatible Input Pins (Note 1) Input Current TENA TTL Compatible Input Pin: with Pull-Down Resistor IIH IIL with Pull-Down Resistor removed in Standby Mode CMOS COMPATIBLE INPUTS CMOS Compatible Input Voltage Low State High State Input Current (Pin X1) TTL/CMOS COMPATIBLE OUTPUTS TTL/CMOS Compatible Output Voltage Low State (Note 2) Low State (Note 3) TTL/CMOS Compatible Output Voltage High State (Note 4) High State (Note 5) High State (Note 2) Three State Output Leakage Current Characteristic TWISTED PAIR RECEIVER INPUTS Input Voltage Range (DC + AC) Differential Input Squelch Threshold Voltage (MC68160, MC68160C) Differential Input Squelch Threshold Voltage (MC68160B) Common Mode Bias Generator Voltage Common Mode Input Resistance Differential Input Resistance TWISTED PAIR TRANSMITTER OUTPUTS Differential Output Voltage Pre-Emphasis Level Signal Level (MC68160, MC68160C) Signal Level (MC68160B) Common Mode Output Voltage Range Common Mode Output Voltage in Standby Mode Note 7 VODFTPP VODFTPS VODFTPS VOCMTP VOCMTPSB 2.2 1.56 1.38 Note 6 IOH = -100 A 0 VDD - 1.0 2.8 1.98 1.98 4.0 VDD V V V VITP VITPSQ VITPSQ VBCMTP RCMTP RDIFFTP - Note 10 Note 10 Note 9 - - 1.5 270 260 1.8 1000 2.5 4.3 390 400 3.2 - - V mV mV V k VOL IOL = 4.0 mA IOL = 10 mA VOH IOH = - 500 A IOH = - 10 mA IOH = - 4.0 mA 0 V VOZ VDD Test Conditions - - 3.9 3.9 2.4 - Min 0.45 0.45 V - - - 10 Max A Unit V - VIL(CMOS) VIH(CMOS) IIH & IIL - 3.0 0 V < VI < VDD - 1.0 - 100 A V - VIL(TTL) VIH(TTL) 0 V < VI < VDD - 2.0 - 0.8 - 10 A V Symbol Test Conditions Min Max Unit
IIH IIL IIH & IIL
- - -
+200 - 20 10
IOZ Symbol
NOTES: 1. APORT, TPAPCE, CS0, CS1, CS2, TX, LOOP, TPFULDL, TPSQEL and TPEN (In Input Mode). 2. TCLK, RX, RCLK, RENA and CLSN. 3. TPPLR, TPLIL, TPJABB, TXLED, RXLED, CLLED and TPEN (In Output Mode). 4. TPPLR, TPLIL, CLLED, TXLED and RXLED. 5. TPJABB and TPEN (In Output Mode). 6. Measured with Test Load B1 (shown in Figure 3), applied directly to the TPTX+/- pins of the device. 7. Measured differentially with Test Load B2 (shown in Figure 4), applied directly to the TPTX+/- pins of the device. 8. Measured directly on the TPTX+/- pins of the device. 9. Measured with Test Load B3 (shown in Figure 5), applied directly to the TPRX+/- pins of the device. 10. The Common Mode Input Voltage is between 1.8 V and 3.2 V.
MOTOROLA ANALOG IC DEVICE DATA
9
MC68160 MC68160B MC68160C
DC ELECTRICAL CHARACTERISTICS (continued) (TA = 25C, VCC = 5.0 V 5%. Unless otherwise noted, minimum and maximum
limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160, B, C except where noted.) Characteristic TWISTED PAIR TRANSMITTER OUTPUTS Differential Output Voltage IDLE Mode Open Circuit Differential Output Impedance TRANSMISSION Mode IDLE Mode Common Mode Output Impedance TRANSMISSION Mode (MC68160, MC68160C) TRANSMISSION Mode (MC68160B) IDLE Mode VODFTPI VODFTPO RODFTPT RODFTPI Note 8 ROCMTPT ROCMTPT ROCMTPI 3.0 2.5 1.0 7.0 7.0 10 k Note 6 Note 8 Note 8 12 8.0 28 29 - - 50 5.25 mV V Symbol Test Conditions Min Max Unit
NOTES: 1. APORT, TPAPCE, CS0, CS1, CS2, TX, LOOP, TPFULDL, TPSQEL and TPEN (In Input Mode). 2. TCLK, RX, RCLK, RENA and CLSN. 3. TPPLR, TPLIL, TPJABB, TXLED, RXLED, CLLED and TPEN (In Output Mode). 4. TPPLR, TPLIL, CLLED, TXLED and RXLED. 5. TPJABB and TPEN (In Output Mode). 6. Measured with Test Load B1 (shown in Figure 3), applied directly to the TPTX+/- pins of the device. 7. Measured differentially with Test Load B2 (shown in Figure 4), applied directly to the TPTX+/- pins of the device. 8. Measured directly on the TPTX+/- pins of the device. 9. Measured with Test Load B3 (shown in Figure 5), applied directly to the TPRX+/- pins of the device. 10. The Common Mode Input Voltage is between 1.8 V and 3.2 V.
DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended
ambient operating temperature and power supply voltage ranges for each MC68160, B, C except where noted.) Characteristic AUI RECEIVER INPUTS Input Voltage Range (DC + AC) Differential Mode Input Voltage Range Differential Input Squelch Threshold Voltage (MC68160, MC68160C) Differential Mode Input Voltage Range (MC68160B) Common Mode Input Resistance Differential Input Resistance (ARX, ACX Inputs) AUI TRANSMITTER OUTPUTS Common Mode Output Voltage IDLE Mode ACTIVE Mode STANDBY Mode Differential Output Voltage IDLE Mode ACTIVE Mode Differential Output Load Current IDLE Mode Output Short Circuit Current Figure 6 VOCMIA VOCMAA VOCMSA VODFIA VODFAA IODFIA IODSA Figure 7 - Output Short Circuited to VDD or GND - 4.0 150 mA IO = -100 A Figure 6 - 600 40 1315 mA 1.0 1.0 VDD - 2.0 4.2 4.2 VDD - 1.2 mV V VIA VIDFA VIASQ VIASQ RICMA RIDFA - - - - 1.0 V < VICMA < 4.2 V 1.0 V < VICMA < 4.2 V 318 mV < VIDMA < 1315 mV 1.0 318 - 275 - 300 1.5 5.0 4.2 1315 -175 -175 - - V mV mV mV k k Symbol Test Conditions Min Max Unit
10
MOTOROLA ANALOG IC DEVICE DATA
MC68160 MC68160B MC68160C
Figure 3. Test Load B1 Figure 4. Test Load B2
Device
V1
39 RCM 1.0 k 39
+ VCMD -
Device
39 39
100
Figure 5. Test Load B3
Device
39 39
RCM 10 k
+ VCMD -
NOTE:
A total of 50 per driver output is required for proper series line termination. This is realized with the 39 external resistors shown in Figures 3, 4 and 5, together with the internal driver output resistance.
Figure 6. AUI Common Mode Termination
- 39 39 + IO VCM VDIFF
Figure 7. AUI Differential Output Short Circuit Current
IOD
MOTOROLA ANALOG IC DEVICE DATA
11
MC68160 MC68160B MC68160C
AC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended
temperature and power supply voltage ranges for each MC68160, B, C except where noted.) Characteristic EXTERNAL CLOCK INPUT (X1) Cycle Time (Note 1) (See Figure 8) Fall Time Rise Time Low Time High Time RECEIVE PHASE-LOCKED-LOOP SWITCHING Stabilization Time CONTROLLER TRANSMIT SWITCHING (MOTOROLA MODE) TCLK Cycle Time TCLK High Time TCLK Low Time TCLK Rise and Fall Time TX Setup Time to TCLK TX Hold Time to TCLK TENA Setup Time to TCLK TENA Hold Time to TCLK CONTROLLER RECEIVE SWITCHING RCLK Cycle Time RCLK High Time RCLK Low Time (MC68160, MC68160C) RCLK Low Time (MC68160B) RCLK Rise and Fall Time RX Hold Time from RCLK RX Set-Up Time to RCLK RCLK Delay from RENA RX Delay from RENA RENA Deassertion Delay from RCLK (See Figure 12)
NOTES: 1. To meet IEEE-802.3 specifications. 2. Load on specified output is 20 pF to ground, unless otherwise noted. 3. = Rising Edge
Symbol
Min
Max
Unit
t1 t2 t3 t4 t5 t7 t10 t11 t12 t13 t14 t15 t16 t17
49.995 - - 20 20
50.005 5.0 5.0 30 30
ns
-
100
ms
99 45 45 - 20 0 20 0
101 55 55 8.0 - - - -
ns
ns ns
t20 t21 t22 t22 t23 t24 t24.1 t25 t26 t27
90 42 47 44 - 10 70 - - 10
- - 55 58 8.0 - - 650 600 30
ns
ns ns ns
Figure 8. X1 Input Voltage Levels for Timing Measurements
t1 4.0V 1.5V 0V t5 t2 3.6V 1.5V 0.4V t4 t3 1.5V 0.4V 3.6V
12
MOTOROLA ANALOG IC DEVICE DATA
MC68160 MC68160B MC68160C
Figure 9. Receive Phase-Locked-Loop Switching
CS0 D CS1 D CS2
1.5V
TPRX t7 1.5V RENA
NOTE: CS0 * CS1 * CS2 is the logical AND operation and refers to the pins not at Logic 1.
Figure 10. Transmit Timing (Motorola Mode)
t11 3V t13 t13
1.5V TCLK
1.5V
0.8V
3V
1.5V t10
1.5V
1.5V
1.5V t17 1.5V
t16 1.5V TENA
t12
t14
t15
TX 1.5V 1.5V
Figure 11. Receive Timing (Motorola Start of Frame)
1.5V RENA t25 1.5V RCLK t26 RX 1.5V 3V 0.8V t24.1 3V 1.5V 0.8V t24 1.5V 1.5V 1.5V 1.5V t23 t23 t22 t21
t20
MOTOROLA ANALOG IC DEVICE DATA
13
MC68160 MC68160B MC68160C
Figure 12. Receive Timing (Motorola End of Frame)
RENA 1.5V t27
1.5V RCLK
RX Last Bit CONTROLLER TRANSMIT SWITCHING (Intel Mode - Support by MC68160 Only) Characteristic TXC Cycle Time TXC High and Low Time TXC Rise and Fall Time TXD Setup Time to TXC TXD Hold Time to TXC RTS Setup Time to TXC RTS Hold Time to TXC CONTROLLER RECEIVE SWITCHING RXC Cycle Time RXC High Time RXC Low Time RXC Rise and Fall Time RXD Hold Time from RXC RXD Set-Up Time to RXC CRS Delay from RXC
NOTE: Load on specified output is 20 pF to ground, unless otherwise noted. = Rising Edge = Falling Edge
Symbol t40 t41 t42 t43 t44 t45 t46
Min 99 40 - 20 0 20 0
Max 101 - 5.0 - - - -
Unit ns
ns ns
t80 t81 t82 t83 t85 t85.1 t86
90 45 40 - 50 35 12
- 55 - 5.0 - - 30
ns
ns
Figure 13. Transmit Timing (Intel)
t42 TXC t42 t41 3V
3V
0.8V
1.5V
1.5V
1.5V
1.5V t40
1.5V
1.5V t46 1.5V
t45 RTS 1.5V
t41
t43 TXD 1.5V 1 0 0 0 1.5V
t43
t44 1.5V 1 Last Bit 1/0
14
MOTOROLA ANALOG IC DEVICE DATA
MC68160 MC68160B MC68160C
Figure 14. Receive Timing (Intel)
CRS 1.5V
t81 t80 1.5V RXC 1.5V
t82 1.5V 1.5V .8V t83
t86 3V 3V
t83
t85.1 RXD 1.5V 1.5V
t85
CONTROLLER TRANSMIT SWITCHING (Fujitsu Mode - Supported by MC68160 Only) Characteristic TCKN Cycle Time TCKN High and Low Time TCKN Rise and Fall Time TXD Setup Time to TCKN TXD Hold Time to TCKN TEN Setup Time to TCKN TEN Hold Time to TCKN CONTROLLER RECEIVE SWITCHING RCKN Cycle Time RCKN High Time RCKN Low Time RCKN Rise and Fall Time RXD Hold Time from RCKN RXD Set-Up Time RCLK RCKN Delay from XCD XCD Deassertion Delay from RCKN (See Figure 17)
NOTE: Load on specified output is 20 pF to ground, unless otherwise noted. = Rising Edge = Falling Edge
Symbol t90 t91 t92 t93 t94 t95 t96
Min 99 45 - 20 0 20 0
Max 101 55 8.0 - - - -
Unit ns
ns ns
t100 t101 t102 t103 t104 t104.1 t105 t106
90 40 45 - 50 35 - 0
- - 55 8.0 - - 600 -
ns
ns
ns
Figure 15. Transmit Timing (Fujitsu)
t90 TCKN 1.5V t95 t91 1.5V TEN 1.5V 1.5V 1.5V 0.8V t92 t91 3V
0.8V t92
1.5V t96
1.5V
t93 1.5V TXD
t94 1.5V
MOTOROLA ANALOG IC DEVICE DATA
15
MC68160 MC68160B MC68160C
Figure 16. Receive Timing (Fujitsu Start of Frame)
1.5V XCD t105
t101 3V 0.8V t100 1.5V 1.5V
RCKN 1.5V 1.5V 1.5V t104.1 t104 1.5V
t102 RXD 1.5V
t103
t103
Figure 17. Receive Timing (Fujitsu End of Frame)
XCD 1.5V
t106
1.5V RCKN
RXD CONTROLLER TRANSMIT SWITCHING (National Mode - Supported by MC68160 Only) Characteristic TXC Cycle Time TXC High and Low Time TXC Rise and Fall Time TXD Setup Time to TXC TXD Hold Time to TXC TXE Setup Time to TXC TXE Hold Time to TXC CONTROLLER RECEIVE SWITCHING RXC Cycle Time RXC Low Time RXC High Time RXC Rise and Fall Time RXD Hold Time from RXC RXD Set-Up Time from RXC RXC Delay from CRS CRS Deassertion Delay from RXC RXC continuing beyond CRS
NOTE: Load on specified output is 20 pF to ground, unless otherwise noted. = Rising Edge = Falling Edge
Symbol t110 t111 t112 t113 t114 t115 t116
Min 99 45 - 20 0 20 0
Max 101 55 8.0 - - - -
Unit ns
ns ns
t120 t121 t122 t123 t124 t124.1 t125 t126 t127
90 40 40 - 50 35 - 0 5.0
- - 60 8.0 - - 600 15 -
ns
ns
ns cycles
16
MOTOROLA ANALOG IC DEVICE DATA
MC68160 MC68160B MC68160C
Figure 18. Transmit Timing (National)
t111 t110 1.5V t111 t115 1.5V TXE t113 t114 1.5V 0.8V 3V 0.8V 1.5V t116 t112 t112 1.5V
1.5V TXC
1.5V TXD
1.5V
Figure 19. Receive Timing (National)
1.5V CRS t125 t122 t120 1.5V 1.5V 3V 0.8V 1.5V 1.5V t126
1.5V
t127 1.5V
RXC
t121
t123
t123
t124.1 t124 1.5V
RXD
MOTOROLA ANALOG IC DEVICE DATA
17
MC68160 MC68160B MC68160C
TP TRANSMIT SWITCHING Characteristic TPTX Common Mode AC Output Voltage (Note 3) TX to TPTX Steady State Propagation Delay (Note 2) (See Figure 24) Bit Duration Center-to-Center Half-Bit Cell Duration Center-to-Boundary TENA Assert to RENA Assert Delay (Note 7) (See Figure 24) Internal Loopback Delay from TX to RX (Note 7) (See Figure 24) (MC68160, MC68160C) (MC68160B) TPTX End of Packet Hold Time from last positive TPTX Signal Edge to +585 mV Differential Output Level (Note 5) (See Figure 25) TPTX Precompensation Pulse Width (Notes 2 and 6) (See Figure 25) (MC68160, MC68160C) (MC68160B) RENA Deassert Delay from TENA Deassert when Receiver is inactive Motorola Mode (MC68160, MC68160C) Motorola Mode (MC68160B) Fujitsu Mode (MC68160 Only) National Mode (MC68160 Only) Intel Mode (Note 4) (See Figure 26) (MC68160 Only) TPTX Data-to-Link Test Pulse (Note 2) (See Figure 27) TPTX Link Test Pulse Width (Note 2) TPTX Link Test Pulse Decay-to-Idle Condition (Note 1) TPTX Link Test Pulse to next Link Test Pulse (Note 2)
NOTES: 1. 2. 3. 4. 5. 6. 7.
Symbol VOCMTP t130 t131 t132 t133 t134 t134 t135
Min - - 98 48 - - - 250
Typ - - - - - - - -
Max 50 200 102 52 400 450 650 400
Unit mVrms ns
ns ns
ns ns
t136 t136 t137 t137 t137 t137 t138 t139 t140 t141 t142
- - 250 250 250 250 250 8.0 80 80 8.0
45-58 38-58 - - - - - - - - -
- - ns 450 500 450 450 450 24 240 240 24 ms ns ns ms
Measured differentially across the output of Test Load A which is connected directly to the TPTX+/- pins of the device. Measured differentially across the output of Test Load D shown in Figure 23 which is connected directly to the TPTX+/- pins of the device. Measured across the output of Test Load C which is connected directly to the TPTX+/- pins of the device. Same as t137 except the logic states for TENA and RENA are inverted. Measured across the output of Test Load B shown in Figure 21. Measured at the +/-90% points of the precompensation voltage feature of the waveform. (The 0% reference is 0 V differential.) Load on specified output is 20 pF to ground.
Figure 20. Test Load A
Figure 21. Test Load B
100H 39 39 100pF 1.0H 1.0H 100pF 100 VOUT Device 39 39 100
Figure 22. Test Load C
200H 39 39 Vout 47.5 47.5 49.9 VCM
Figure 23. Test Load D
200H 39 100 39 VOUT
NOTE:
A total of 50 per driver output is required for proper series line termination. This is realized with the 39 external resistors shown in Figures 20 to 23, together with the internal driver output resistance.
18
MOTOROLA ANALOG IC DEVICE DATA
MC68160 MC68160B MC68160C
Figure 24. TPTX Transmit Timing (Start of Frame) Switching
X1 TCLK TENA 1.5V 1.5V
TX 1.5V RENA
1 t133
0 1.5V t134 1.5V 1
1
0
0
1
1
RX
0
1
0
0
1
1
TPTX +/- Differential (Logic Levels)
1
0 t130
1
0
0 t131
1 t132
1
TPTX +/- Differential (Pre-Emphasis)
1
0
0V
1
0
0
1
1
Figure 25. TPTX Transmit Timing (End of Frame) Switching
t136 t135
90% TPTX +/- Differential
90% +585mV +585mV
Figure 26. RENA Deassert Delay from TENA
t137 TENA 1.5V
RENA 1.5V
MOTOROLA ANALOG IC DEVICE DATA
19
MC68160 MC68160B MC68160C
Figure 27. TPTX+/- Link Pulse Timing
t142 t141 t140 t139 585mV 585mV 585mV
50mV
TP TRANSMIT JABBER SWITCHING Characteristic Max Length of Transmission before Assertion of TPJABB to indicate Jabber Condition CLSN to indicate Jabber Condition Time from End of Jabber Condition to Deassertion: of TPJABB of CLSN TP TRANSMIT SIGNAL QUALITY ERROR TEST SWITCHING CLSN (Signal Quality Error Test) (See Figure 29) Assertion from last positi e TPTX edge positive Deassertion from last positive TPTX edge Pulse Width TPSQEL Disable Delay Time (See Figure 29)
NOTE:
Symbol t160 t161 t162 t163
Min 20 20 500 500
Max 60 60
Unit ms
ms 750 750
s t170 t171 t172 t173 0.6 06 - 0.5 - 1.6 16 3.1 1.5 40 ns
The load attached to the specified output is a 20 pF capacitor connected to ground, unless otherwise noted.
Figure 28. TPJABB Switching
TPTX (Differential)
-585mV
585mV
t160
t162
1.5V TPJABB t161 1.5V CLSN t163
1.5V
1.5V
20
MOTOROLA ANALOG IC DEVICE DATA
MC68160 MC68160B MC68160C
Figure 29. TPTX SQE (CLSN) Timing (End of Frame)
TPTX+/- 2V
1.5V TPSQEL t173 t171 t170 1.5V CLSN t172 1.5V
TP RECEIVE SWITCHING Characteristic Differential Input Voltage Range Unconditional Squelch (Note 1) (1.8 V < Input Common Mode Voltage < 3.2 V) Positive or Negative Differential Input Pulse Width for Conditional Receive Unsquelch (See Figure 31) TPRX to RCLK Bit Loss at start of packet (See Figure 32) TPRX to RCLK Steady State Propagation Delay (See Figure 32) TPRX to RX Start Up Delay (See Figure 32) TPRX held high from last valid positive transition (See Figure 33) RENA Deassertion Delay from last valid positive transition of TPRX Pair (MC68160, MC68160C) (See Figure 33) RENA Deassertion Delay from last valid positive transition of TPRX Pair (MC68160B) TP RECEIVE LINK INTEGRITY SWITCHING Required Pulse Width Range to be recognized as a Link Pulse (Note 2) Last TPRX activity to high state TPLIL Output (Receive Link Loss Timeout Interval) Receive Link Beat Separation Minimum Range (Note 3) Maximum Range (Note 4)
NOTES: 1. 2. 3. 4.
Symbol VIDFSTP t180 t181 t182 t183 t186 t187 t187
Min 0 20 - - - 230 - -
Max |264| 30 10 400 1.5 - 350 400
Unit mV ns Bits ns s ns ns ns
t200 t201
50 100
200 150
ns ms ms
t202 t203
3.0 100
7.0 150
Measured with Test Load H attached to the receive pins. Measured at the receive pins. Link beats closer in time to this range of values are considered noise, and are rejected. Link beats further apart in time than this range of values are not considered consecutive, and are rejected.
Figure 30. Test Load H
1.0H 100 100pF 1.0H 100pF
Figure 31. TPRX Input Switching
200H t180 Line TPRX -330mV t180 0mV +330mV
MOTOROLA ANALOG IC DEVICE DATA
21
MC68160 MC68160B MC68160C
Figure 32. TPRX Receive Timing (Start of Frame)
1 TPRX+/- 0V -300mV
Bit n 0 0V
Bit n+1 1
Bit n+2 0
Bit n+3 1
Bit n+4 1
t182 RENA t183 t181 1.5V RCLK 1.5V
RX
Bit n
Bit n+1
Bit n+2
Figure 33. RENA Deassertion Delay from Last Valid Positive Transition of TPRX Pair
t186 +300mV TPRX+/- t187 RENA 1.5V +300mV 0V
Figure 34. TP Receive Link Integrity Switching
t202/t203 t200
300mV
300mV
TPRX
t201
50% TPLIL
22
MOTOROLA ANALOG IC DEVICE DATA
MC68160 MC68160B MC68160C
TP COLLISION SWITCHING Characteristic Time from collision (TPRX activity caused assertion of RENA followed by assertion of TENA) to assertion of CLSN Time from end of collision (Deassertion of TENA with uninterrupted TPRX pair activity) to deassertion of CLSN TP FULL DUPLEX SWITCHING TPFULDL assert to collision detect disable (See Figure 36) TPFULDL deassert to collision detect enable TPFULDL assert to data loop back disable (See Figure 37) TPFULDL deassert to data loop back enable
NOTE: Load on specified output is 20 pF to ground, unless otherwise noted.
Symbol t210 t211
Min - 350
Max 300 900
Unit ns
t220 t221 t222 t223
- - - -
50 50 350 150
ns ns
Figure 35. TPTX Collision Timing
RENA
1.5V TENA t210
1.5V
t211
1.5V CLSN
1.5V
Figure 36. TPTX Full Duplex Timing
TPFULDL 1.5V 1.5V
t220 CLSN 1.5V
t221
1.5V
Figure 37. TPTX Full Duplex Timing
TPFULDL 1.5V 1.5V
RENA
t223 1.5V
t222 1.5V
MOTOROLA ANALOG IC DEVICE DATA
23
MC68160 MC68160B MC68160C
AUI TRANSMIT SWITCHING Characteristic TCLK to ATX Pair Steady State Propagation Delay Output Differential Rise and Fall Times (Measured directly at device pins) ATX Bit Cell Duration center-to-center (Measured directly at device pins) ATX Half-Bit Cell Duration center-to-boundary (Measured directly at device pins) ATX Pair Held at Positive Differential at start of Idle (Measured through transformer)
NOTE: Load on specified output is a shunt 27 H inductor and 83 resistor.
Symbol t240 t241 t242 t243 t244
Min - 1.0 - - 200
Typ - - 99.5-100.5 49.5-50.5 -
Max 100 5.0 - - -
Unit ns ns ns ns ns
Figure 38. ATX Transmit Timings
TCLK
1.5V
TENA 1 t240 0 1 0 0 t241 90% ATX+/- Differential (Logic Levels) 0V 1 0 1 0 10% t242 t243 0 1 1 t241 90% 1 10% 0V 1 t244 70%
TX
AUI RECEIVE SWITCHING Characteristic ARX/ACX Differential Input Voltage Range ARX/ACX Differential Input Pulse Width to: Initiate Data Reception Inhibit Data Reception RENA Assertion Delay RENA Deassertion Delay Symbol - t261 t262 t266 t267 Min 318 30 - - - Max 1315 - 18 100 450 ns Unit mV ns
Squelching Characteristics The receive data pairs and the collision pairs should have the following squelch characteristics: 1. The squelch circuits are on at idle (with input voltage at approximately 0 V differential). 2. If an input is in squelch, pulse is rejected if the peak differential voltage is more positive than -175 mV, regardless of pulse width. 3. A pulse is considered valid if its peak differential voltage is more negative than -300 mV and its width, measured at -285 mV, is > 25 ns. 4. The squelch circuits are disabled by the first valid negative differential pulse on either the AUI receive data or collision pair. 5. If a positive differential pulse occurs on either the AUI receive data or collision pair > 175 ns, end of frame is assumed and squelch circuitry is turned on.
Figure 39. ARX/ACX Timing
+175mV ARX+/- ACX+/- Differential Input Voltage
-175mV t261/ t262
24
MOTOROLA ANALOG IC DEVICE DATA
MC68160 MC68160B MC68160C
Figure 40. ARX/ACX Timing
Bit Q ARX+/-/ ACX+/- Differential Input Voltage -300mV
Bit U
Bit V
Bit W t260
Bit X
Bit Y t260
Bit Z
t261 -40mV 1 -275mV 0 1 0
+300mV 90% 0 10% 90% 1 10% 0V 1
t266
t267
1.5V RENA/CLSN RCLK
1.5V
RX Bit Q Bit U Bit V Bit U Bit X Bit Y Bit Z
FUNCTIONAL DESCRIPTION
Introduction The MC68160, B, C (EEST) was designed to perform the physical connection to the Ethernet media. This is done through two separate media dependent interfaces and a SIA interface. The media dependent interfaces are the Attachment Unit Interface(AUI) and the 10BASE-T Twisted Pair(TP) port. The MC68160's SIA interface is compatible with most industry controllers and selected by three mode control pins. The MC68160B's and MC68160C's SIA interface supports the Motorola MC68360 only. Chip status is supported on all versions indicated by the condition of 6 status indicator pins. All but one are open collector outputs. If the EEST isn't receiving data, the controller may initiate transmission. NRZ data from the communications controller SIA interface is encoded by the MC68160, B, or C into Manchester Code in preparation for transmission on the media. The data is then applied to either the AUI or TP port. If the data was transmitted using the 10BASE-T port, this data is also looped back to the receive data interface SIA pins connected to the controller. This allows detection of a collision condition in the event that another station on the media attempted transmission at the same time. After the entire data frame has been transmitted, the EEST must force the media idle signal. The idle signal frees the media for other stations that have deferred transmission. If no other transmissions are required the link enters an idle state. During this idle state the 10BASE-T transmitter issues idle pulses which communicates to the receiver connected to the other side that the link is valid. If the transmitter connected at the other end begins transmission, the EEST will assert a receive enable signal, and forward the received data to the controller. Upon reception of data at the 10BASE-T port, the data is screened for proper sequence and pulse width requirements. If the preamble of the received frame meets the requirements, the PLL locks onto the 64-bit preamble and begins to decode the Manchester Code to NRZ code. This code is then presented to the communications controller at the receive data pins at the SIA interface. If data is received at the AUI port, it is sent directly to the communications controller via the SIA interface. Data Transmission To have properly encoded transmit data, the com- munications controller must be synchronized to TCLK. Transmission to the 10BASE-T or AUI media occurs when TENA is asserted and data is applied to the TX pin. Finally, to signify transmission, the TXLED in will cycle on and off at a 100 ms period. Data transmission for EEST is accomplished either over the 10BASE-T port or the AUI port. Both connections to the media are made with industry standard media interface components. The 10BASE-T interface requires a filter and transformer, the AUI interface requires only a transformer. The filter for the 10BASE-T transmit circuit will have to be chosen for each application.
MOTOROLA ANALOG IC DEVICE DATA
25
MC68160 MC68160B MC68160C
If after approximately 40 ms after a TP or AUI transmission has begun, the EEST is still transmitting, the TPJABB pin will assert to signify a jabber condition. Also, the CLLED pin will transition high and low alternately with a 100 ms period. The transmit circuitry is, however, unaffected by the jabber condition, so the communications controller has the responsibility of monitoring and stopping transmission. When transmission is complete, the transmit circuitry will begin the end of transmit and decay to idle responses necessary to meet requirements of the 802.3 standard for the TP and AUI port. Data Reception Other than the case of being in Loop Back mode, data reception to the RX pin of the EEST is initiated by signaling at the RX+/- or AUI ARX+/- pins. If at the TP port, the data is screened for validity by checking for sequence and pulse width requirements, then passed to the decode and receive circuitry. The RENA pin asserts and the data and corresponding clock is passed to the communications controller. After the frame has been transmitted, the MC68160, B and C detects the ending transmission and negates RENA. If at the AUI port, the data is checked for proper pulse width requirements before being passed to the decode circuitry. If the data pulses are longer than at least 20 ns, RENA gets asserted and the frame is decoded to RX with and accompanying RCLK output. Collision Collision is the occurrence of simultaneous transmit activity by two or more stations on the network. In the event of collision, the data transfer paths are unaffected. If the MC68160, B and C is in the twisted pair mode, collision is detect by simultaneous receive and transmit activity. If in the AUI mode, collision is detected by activity on the ACX+/- pins. In either case, if collision is detected, the CLSN pin will assert to notify the communications controller. Jabber The EEST has a jabber timer to detect the jabber condition. In the event that the transmitting station continues to transmit beyond the allowable transmit time, a jabber timer (40 ms) will expire and assert the TPJABB pin to alert the communications controller of the situation. The TPJABB pin can source or sink up to 10 mA, and so, is capable of driving a status LED. In the AUI mode, the pin is driven to high impedance since the transceiver connected to the AUI port must alert the communications controller of the jabber condition. Full Duplex A feature unique to the MC68160, B and C is the Full Duplex mode. In this mode the EEST is capable of transmitting and receiving simultaneously. Collision conditions are not announced and internal loop back is disabled. The remainder of the EEST functionality remains unchanged from the non-Full Duplex mode. Full Duplex mode is enabled by asserting the TPFULDL pin. Auto Port Selection If the APORT pin is asserted, the MC68160, B and C will automatically select the TP or AUI port depending on the presence of valid link beats or frames at the TP RX+/- pins. If the AUI port is automatically selected by another transmitting station or by setting TPEN low, the TP transmit port of the EEST continues to transmit link beats to keep the link active. Auto Polarity Selection If the RX+ and the RX- wires happen to get reversed, the MC68160, B and C has the ability to automatically reverse the pins internally so that the received data is valid. In addition, an open collector status pin (TPPLR) is driven low to indicate the fault. In the AUI or reset mode this pin presents a high impedance. Loop Back Mode To test the transmit and receive circuitry without disturbing the connected network, the EEST has a Loop Back mode. Loop Back mode routes transmit data and clock to the receive data and clock pins using as much of the transmit and receive circuitry as possible. This gives a test of the MC68160, B and C Manchester encode and decode function. LOOP must not be asserted when TPFULDL pin is asserted. This causes the MC68160, B and C to enter a test mode. This test mode is used during final test and is not intended to be entered under normal operation (see Application Notes section).
26
MOTOROLA ANALOG IC DEVICE DATA
MC68160 MC68160B MC68160C
APPLICATIONS INFORMATION
Selection of Crystal and External Components Accuracy of frequency and stability over temperature are the main determinants of crystal choice. Specifications for a suitable crystal are tabulated below.
Vendor Part #
FEE Fil-Mag Valor Electronics Pulse Engineering TOKO
78Z1120B-01, 78Z1122B/D-01, 78Z1122 F-01 PT3877, FL1012, FL1066 PE-65434, PE65424, PE65433 PM01-00, PM02-00, PM05-00
AAAAA A AAAAAAAAAAAAAAAAA A AAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A AAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAA
Frequency Mode 20.000 MHz Fundamental 100 ppm 100 ppm Tolerance Stability Aging 5 ppm/yr 7.0 pF Shunt Capacitance Load Capacitance 18-20 pF 25 Series Fundamental Resistance (ESR) Drive Level 500 W X1 X2
AUI Transformer Choice Like the 10BASE-T outputs, the AUI differential outputs are low impedance sources and capable of meeting the IEEE 802.3 waveform requirements when a coupling transformer is used. Some AUI transformer vendors and their products are provided below.
Vendor Part #
Coilcraft FEE Fil-Mag Valor Electronics Pulse Engineering TOKO
LAX-ET304 23Z90, 23Z91/ 23Z92 LT6032, LT6033 PE64502, PE6103 Q30ALQ8-1AA3, Q30ALQ9-1AA3 Q30ALQ8 1AA3 Q30ALQ9 1AA3
A suitable crystal is the MTRON HC49 MP-1, 20.000 MHz crystal. 20 pF for C4 and C5 have been shown to work reliably.
1 C5
2 C4
PLL Filter Components The filter components at Pin 12 were chosen to assure adequate pull-range but with a emphasis on stability. It is not foreseeable that a design would need to change the components, but for the sake of completeness, relevant values are provided here. VCO Gain
+ 24
MHz and, Volt * sec
Phase Detector Gain
+ 100 p2 )
mA
rad
and the
filter impedance function is; (jw 1 C6) (for C6 Z(jw) jw * C5 * (jw 1 C5)
[
)
uu C5)
10BASE-T Filter and Transformer Choice The MC68160, B and C differential outputs are low impedance voltage sources. Therefore, external series resistors must be used in order to match the characteristic impedance of twisted pair. Since the output resistance of each leg of the transmitter is about 10 , a 39 resistor is used in series as shown in the applications schematic. So the impedance presented from the source to the isolation transformer is then very nearly 100 . The following is a list of some 10BASE-T filter module vendors and their products.
Application Notes: The following procedure is applicable to all three versions MC68160, MC68160B and MC68160C. References to the MC68160 includes all the versions. Resetting the MC68160 after power up. In some applications, after initial power up, the MC68160 may not be able to transmit or receive data. This is usually caused by the LOOP and TPFULDL control lines being active at the same time. This is an illegal condition during normal operation, it places the MC68160 into the production test mode. To exit the test mode and return to normal: Set LOOP low, TPFULDL high and TPSQEL low. Then, while keeping TPSQEL low, raise LOOP after 300 ms lower TPFULDL. This will put the MC68160 into test mode but also resets the MC68160. After 500 ms lower LOOP to get out of the test mode. TPFULDL may then be de-asserted if desired. The MC68160 is now ready for operation. A hardware implementation of this fix would be to place a pull down resistor on the TPSQEL pin. Even if test mode is entered by accident, this ensures that zero's will be written to the test register. The hardware implementation will solve the problem if the test mode is entered because of noise on the TPSQEL pin. If the controller is toggling the MC68160 lines while it is booting up, the reset procedure must be followed.
MOTOROLA ANALOG IC DEVICE DATA
27
Figure 41. Typical Application Diagram
VDD
TX
CLSN
TENA
TCLK
TPEN
RCLK
TPLIL
TPPLR
CLLED
TPJABB
RXLED
TXLED
RX VDDPWR TPTX+ TPTX- VDDPWR GNDPWR 34 33 32 31 30 29 28 27 VCC R3 100 35 R2 39 VDD 36 39 CTP2 0.01F 37 R1 1 2 CS0 CS1 CS2 LOOP VDDDIG GNDANA TPRX+ TPRX- VDDANA TPAPCE TPFULDL ACX- ACX+ ARX- ARX+ ATX- ATX+ TPSQEL VDDVCO GNDDIG
AMD (7990/79C900) Intel (825** -86/90/93/96) Fujitsu (869** -50/60) National (8390/83C90/83932B) 3 4 5 6 VDD 7 3 4 5
GNDCTL
X1
X2
VDDDIG
GNDDIG
VCC 300 VCC 20MHz C4 20pF VDD 3900pF C3 20pF X1 C5 0.039 F C6 TPSQEL TPFULDL TPAPCE R 12
14 15
GNDVCO
16 17
18 19
20
GNDSUB
Power Supply Bypassing
21 22 23 24 25 26 R 15 10 K
9 APORT VCC 10 VDDDIV 11 VDDFM 12 MFILT 13 GNDFM
10 F
0.1 F
IIIIII IIIIII IIIIII
8
CTP3 0.01F
(Example of PE-65424)
7 0.1 F C2 R6 39 R7 39
AUI XFMR
1
1
1
Standby Low Current Mode
IIIIII IIIIII IIIIII
28
LED5 LED3 R8 330 R9 330 R 11 330 R 13 330 R 14 330 LED6 R 33 330 LED2 LED1
Figure 41.
COMMUNICATIONS CONTROLLER
CLSN RCLK Collision Int Receive Clock
TPEN TCLK TENA TX LED4
TP Enable Transmit Clock Transmit Enable Transmit Data
MC68360
RENA RX LOOP 52 1 RENA GNDPWR 38 2 39 VDD 51 50 49 48 47 46 45 44 43 42 41 40 APOR AutoPort En Receive Enable Receive Data LoopBack
Valor (PT3877, PT3882, FL1012, FL1066) TOKO (PM01, PM02, PM05) Pulse Engineering (PE-65433, PE-65434, PE-65424) 16 15 14 13 12
+5.0V
1 TD + 2 TD - 3 RD + 6 RD - 6 7 8 11 10 9
MC68160FB, BFB, CFB
RJ45
MC68160 MC68160B MC68160C
Coilcraft (LAX-ET30*) Pulse Engineering (PE-64***) Valor (LT600*/LT603*) TOKO (Q30ALQ*-1AA3) 1 0.1 F C1 R4 39 16 2 15 4 R5 39 13 11 5 12 10 8 9 3 6 11 14 12 9 10
+12V
VDD
1 2 3 4 5 13 6 14 7 15 8
Communications Controller Selection
CS0 1 0 1 0 1 1 0 0 0 0 0 0 Motorola MC68360, AMD 7990 & 79C900 Intel 82586, 82590, 82593, 82596 Fujitsu MB86950, MB86960 National 8390, 83C690, 83932B CS1 CS2 802.3 Communication Controller
10 F
0.1 F
1. For Suitable Crystal (X1) see applications text on previous page.
AUI
MOTOROLA ANALOG IC DEVICE DATA
2. Decoupling capacitors should be placed as close to supply pins as possible.
MC68160 MC68160B MC68160C
OUTLINE DIMENSIONS
FB SUFFIX PLASTIC PACKAGE CASE 848D-03 (TQFP-52) ISSUE C
4X 4X TIPS
0.20 (0.008) H L-M N
0.20 (0.008) T L-M N C L
39
-X- X=L, M, N
52 1
40
AB AB -M- B V
PLATING
G
3X VIEW
Y
-L-
VIEW Y F
BASE METAL
B1
13 14 26 27
J
A1 S1 A S
-N-
0.13 (0.005)
SECTION AB-AB
ROTATED 90_ CLOCKWISE
C -H- -T-
SEATING PLANE
4X
2 0.10 (0.004) T
4X
3 VIEW AA
NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --- 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ --- 0_ 12 _ REF 5_ 13 _ INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --- 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ --- 0_ 12 _ REF 5_ 13 _
0.05 (0.002)
S
W 1 C2
2XR
R1
0.25 (0.010)
GAGE PLANE
K C1 E Z
VIEW AA
DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3
MOTOROLA ANALOG IC DEVICE DATA
EEEE CCC EEEE CCC
M
V1
U
D T L-M
S
N
S
29
MC68160 MC68160B MC68160C
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315
MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 INTERNET: http://www.mot.com/SPS/
30
MOTOROLA ANALOG IC DEVICE DATA
MC68160/D

▲Up To Search▲

Price & Availability of MC68160

	To Download MC68160 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .